1. Field of the Invention
The present invention relates to a thin film transistor-liquid crystal display (hereinafter referred to as a TFT-LCD) and a manufacturing method therefor. More particularly, this invention relates to a TFT-LCD and a manufacturing method therefor which etches multi-layer patterns in a single process step.
2. Description of the Related Art
A conventional TFT-LCD is disclosed in Society for Information Display ""94 DIGEST, page 263, the content of which is hereby expressly incorporated by reference herein in its entirety. That TFT-LCD will now be described with reference to FIGS. 1, 2A-2H, and 3A-3H.
In FIG. 1, a conventional TFT-LCD is depicted which comprises: a substrate 1, a gate electrode 2, an anodic oxidation layer 3, an insulating layer 4, an amorphous silicon layer 5, an n+ amorphous silicon layer 6, a source/drain electrode 9, a passivation layer 10, and a pixel electrode layer 13.
FIGS. 2A-2H show several cross-sectional views depicting different stages of a fabrication sequence for the conventional TFT-LCD shown in FIG. 1. FIGS. 3A-3H show cell views of layouts corresponding to the steps illustrated in FIGS. 2A-2H, respectively. Some layers are omitted from the cell layout views of FIGS. 3A-3H for purposes of simplification. Referring to those figures, a conventional method for fabricating a TFT-LCD generally comprises the steps of:
forming a gate pad 21, a gate electrode 2, and a gate line by depositing and etching a metal layer on a substrate 1;
forming a anodic oxidation layer 3 on both the gate electrode 2 and a portion of the gate pad 21;
depositing an insulating layer 4;
depositing an amorphous silicon layer 5 on the insulating layer 4;
depositing an n+ amorphous silicon layer 6 on the amorphous silicon layer 5;
etching both the amorphous silicon layer 5 and the n+ amorphous silicon layer 6 to form an active island 56;
partially etching the insulating layer 4 on the gate pad 21;
forming both a source/drain electrode 9 and a data line by depositing and etching a metal layer;
forming a passivation layer 10 having a contact hole 12 by depositing and etching an insulating material; and
forming a pixel electrode 13 by depositing and etching a transparent conductive material.
The above-described conventional TFT-LCD has many problems.
First, it reduces production yield. In addition, the etchants used during the etching process steps cause defects in the resulting TFT-LCD.
Moreover, it is more costly because many etching processes are employed in its fabrication.
An objective of the present invention is to provide a TFT LCD and a manufacturing method therefor which etches multi-layer patterns in a single process step. Accordingly, the present invention not only reduces the number of masking processes but also produces a high quality device with less defects.
In order to achieve this objective, a method is provided for manufacturing a TFT-LCD according to the present invention, which comprises the steps of:
depositing a gate metal on a substrate;
forming a gate electrode and a gate pad by etching the gate metal;
depositing an insulating layer;
depositing an amorphous silicon layer;
depositing an n+ amorphous silicon layer on the amorphous silicon layer.
depositing a source/drain layer on the n+ amorphous silicon layer;
etching the source/drain layer, the n+ amorphous silicon layer, and the amorphous silicon layer to form a triple layer pattern in a single process step;
etching the source/drain layer and the n+ amorphous silicon layer to form a source/drain electrode pattern;
depositing a passivation layer;
etching a passivation layer to expose both a portion of the source/drain electrode and a portion of the gate pad;
depositing a pixel electrode on the passivation layer; and
etching the pixel electrode;
A TFT-LCD according to the present invention includes: a gate electrode and a gate pad that are formed on a substrate; an insulating layer having a contact hole exposing the gate pad; an amorphous silicon layer which is formed on the insulating layer; a source/drain electrode which is formed on the amorphous silicon layer; a passivation layer, having contact holes which are formed on both the source/drain electrode and the gate pad; and a pixel electrode layer formed on the passivation layer.